This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-010243, filed Jan. 18, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device formed by cascade-connecting a plurality of diodes, particularly, to an ESD (Electro-Static Discharge) protective circuit of a semiconductor element.
2. Description of the Related Art
In a conventional semiconductor device formed by the CMOS (Complementary Metal Oxide Semiconductor) process, an electrostatic discharge protective circuit (hereinafter referred to as an xe2x80x9cESD protective circuitxe2x80x9d) is arranged in general between the semiconductor element and input-output pins. In general, the ESD protective circuit is formed by cascade-connecting a plurality of diodes.
FIGS. 4A and 4B collectively show a conventional ESD protective circuit; wherein FIG. 4A is a plan view showing the layout of the ESD protective circuit, and FIG. 4B is a cross sectional view showing the construction of the ESD protective circuit. In this example, the ESD protective circuit comprises three diodes 101a, 101b and 101c. 
In the conventional ESD protective circuit, the three diodes 101a, 101b, 101c are substantially equal to each other in size. Also, these diodes 101a, 101b, 101c are laid out in the same direction. In the particular construction, each of the diodes 101a, 101b, 101c, are formed by the standard CMOS process. For example, three N-type well regions 105 are formed in substantially the same size in a surface region of a P-type semiconductor substrate 103. Also, an N+-type diffusion layer 107a and a P+-type diffusion layer 107b are formed in a surface region of each of the N-type well regions 105. In the particular construction, each of the diodes 101a, 101b, and 101c, forms a parasitic bipolar structure including the P-type semiconductor substrate 103.
It should be noted that, among the three diodes 101a, 101b, and 101c, the N+-type diffusion layers 107a in a certain diode are connected to the P+-type diffusion layer 107b of the adjacent diode by a metal wiring 110 via contacts 109. As a result, the three diodes 101a, 101b, and 101c, are cascade-connected to each other. The construction described above with reference to FIGS. 4A and 4B is widely employed in the prior art.
FIG. 5 shows an equivalent circuit diagram of the ESD protective circuit of the construction described above. If, for example, current I0 flows in the forward direction through the diode 101a in the case of the ESD protective circuit described above, a current I01*/(1+xcex2) flows as a base current into the latter stage diode 101b. Also, there is a current I0*xcex2/(1+xcex2) flowing into the P-type semiconductor substrate 103 as the collector current (substrate current) in addition to the base current noted above.
To be more specific, if an electrostatic discharge voltage (ESD voltage) is applied to the input-output pin (not shown), the current flows through the diodes 101a, 101b, 101c in the order mentioned. In this case, a part of the current I0 flowing into the first stage diode 101a connected to the input-output pin is lost as a substrate current I0*xcex2/(1+xcex2). As a result, the current (base current) I0*1/(1+xcex2), which is decreased from the current I0 by the substrate current I0*xcex2/(1+xcex2), flows into the second stage diode 101b. Likewise, the current partly flows into the P-type semiconductor substrate 103 in each of the second stage diode 101b and third stage diode 101c. It follows that the current flowing into the diodes 101b and 101c is gradually decreased.
It should be noted that, in the conventional ESD protective circuit, all the diodes 101a, 101b, and 101c, are equal to each other in size. As a result, these diodes 101a, 101b, and 101c, have the same current capacity. It follows that, since the current is gradually decreased as described above, each of the latter stage diodes 101b, and 101c, has an unnecessary current capacity.
There is no problem in the case where the area occupied by the ESD protective circuit in the chip does not affect the chip size. However, the scaling in the element of the semiconductor device proceeds year by year, with the result that the area of the peripheral circuit including the internal circuit is being made smaller and smaller. On the other hand, the scaling of the ESD protective circuit is not performed in view of the necessity for ensuring a sufficient current capacity, with the result that the area occupied by the ESD protective circuit in the chip is relatively increased. It follows that a serious problem is brought about that the area of the ESD protective circuit affects the chip size. In short, formation of the diodes 101b, 101c, each sized to have an unnecessary current capacity leads to loss of the area.
Suppose that the diodes 101a, 101b, 101c, of the different stages have the same size, and that the same current flows though these diodes 101a, 101b, and 101c. 
In this case, these diodes 101a, 101b, and 101c, are rendered equal to each other in the voltage drop Vf in the forward direction. However, these diodes 101a, 101b, 101c, differ from each other in the current flowing therethrough, as pointed out above. Naturally, these diodes 101a, 101b, 101c, are not equal to each other in the voltage drop Vf. It follows that it is difficult to design the circuit that withstands a high voltage conforming with the sum of the amounts of the voltage drop in respect of the protective capacity.
As described above, the conventional ESD protective circuit is formed of a parasitic bipolar structure manufactured by a CMOS process. However, the conventional ESD protective circuit has the problems that the layout area of the ESD protective circuit occupied in the chip size cannot be decreased, and that it is difficult to achieve the withstand voltage.
According to a first aspect of the present invention, there is provided a semiconductor device, comprising:
a plurality of diodes including a substrate of a first conductivity type biased to a reference potential, a well region of a second conductivity type formed in a surface region of the substrate, and a first diffusion region of the first conductivity type formed in a surface region of the well region;
wherein the plurality of diodes have sizes of at least two kinds and are cascade-connected to each other.